ATA8743-PXQW【PDF 47/238 页】MCU W/TRANSMITTER ASK/FSK 24QFN

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Sheet目录52

43页 44页 45页 46页 [47页]48页 49页 50页 51页

9152BINDCO02/10

ATA8743

14.8 128 kHz Internal Oscillator

The 128 kHz internal Oscillator is a low power Oscillator providing a clock of 128 kHz. The fre-

quency is nominal at 3V and 25癈. This clock may be select as the system clock by

programming the CKSEL Fuses to 0100.

When this clock source is selected, start-up times are determined by the SUT Fuses as shown in

Table 14-9 on page 47.

14.9 System Clock Prescaler

The ATtiny24/44/84 system clock can be divided by setting the Clock Prescale Register

CLKPR. This feature can be used to decrease power consumption when the requirement for

processing power is low. This can be used with all clock source options, and it will affect the

clock frequency of the CPU and all synchronous peripherals. clk

I/O

, clk

ADC

, clk

CPU

, and clk

FLASH

are divided by a factor as shown in Table 14-10 on page 49.

14.9.1

Switching Time

When switching between prescaler settings, the System Clock Prescaler ensures that no

glitches occur in the clock system and that no intermediate frequency is higher than neither the

clock frequency corresponding to the previous setting, nor the clock frequency corresponding to

the new setting.

The ripple counter that implements the prescaler runs at the frequency of the undivided clock,

which may be faster than the CPUs clock frequency. Hence, it is not possible to determine the

state of the prescaler even if it were readable, and the exact time it takes to switch from one

clock division to another cannot be exactly predicted.

From the time the CLKPS values are written, it takes between T1 + T2 and T1 + 2*T2 before the

new clock frequency is active. In this interval, 2 active clock edges are produced. Here, T1 is the

previous clock period, and T2 is the period corresponding to the new prescaler setting.

Table 14-9. Start-up Times for the 128 kHz Internal Oscillator

SUT1..0

Start-up Time from

Power-down and Power-save

Additional Delay from

Reset

Recommended Usage

6 CK

14CK

BOD enabled

6 CK

14CK + 4 ms

Fast rising power

6 CK

14CK + 64 ms

Slowly rising power

Reserved

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